A packet processor receives and processes packets including one or more fields. The packet processor modifies certain fields as a function of other fields and a stored state of the packet processor.
The operations of a packet processor can have dependencies between the operations. Certain orders of execution of the operations satisfy these dependencies while other orders of execution may violate the dependencies. An order of execution that satisfies the dependencies may allow multiple operations to be performed in parallel. An efficient and high-performance packet processor should perform many operations in parallel when possible. However, the resources available for implementing the packet processor might limit the processor's ability to perform operations in parallel.
Exploring alternative implementations of the packet processor generally involves analyzing the possible orders of execution of the operations of the packet processor. However, such analysis can be time-consuming and difficult, because the number of possible orders of execution is an exponential function of the number of different operations of the packet processor.
The present invention may address one or more of the above issues.